The present invention relates to an apparatus with a digital interface suitable for dubbing recording by a network conforming to IEEE 1394 standards, and a digital interfacing method
Recently, image digital processing has been investigated. Also various systems have been under investigation for digital image data recording by a magnetic recording/reproducing device (VTR). For example, in Japan, the Home Digital VTR (Video Tape Recorder) Council has established SD (Standard Definition) standards for recording a SD signal such as an NTSC signal and a PAL signal as it is, namely, as a digital signal by compressing it, and HD (High Definition) standards for recording an HD signal such as an HDTV (High Definition TV) baseband signal as it is, namely, as a digital signal by compressing it. A home digital VTR (hereinafter, called a DVTR) will be commercially availably soon.
Generally speaking, if an image signal is digitized, its information content becomes enormous. Therefore, it is difficult to transmit or record the digitized signal without compressing it, in view of the communication rate and cost. In the case of the SD standards and the HD standards, a digital image signal is compressed in frames.
FIG. 1 is the recording format of a tape conforming to the SD standards.
FIG. 1 shows a recording track 16 formed on the tape 15. As shown in FIG. 1, the recording track 16 comprises a plurality of areas corresponding to various data kinds. That is, the recording track 16 consists of an ITI (Insert and Track Information) including an SSA (Start-Sync Block Area) and TIA (Track ID Area), an audio area, a video area, a subcode area, etc. These areas are sequentially arranged from the bottom edge to the top edge of the tape 15. Gaps 1-3 as well as an amble part are provided between these areas. When the tape is traced by a magnetic head, the ITI, the audio area, the video area and the subcode area are sequentially recorded or reproduced.
The magnetic head traces the tape according to the timing of a head switch pulse shown in FIG. 2. The tape is traced by the rotary head at the rise timing and the fall timing of the head switch pulse in FIG. 2. The head switch pulse is generated synchronously with a frame pulse as shown in FIG. 2. In the case of the SD standards, as shown in FIG. 2, the head traces the tape ten times during one frame period. That is, one frame is recorded on ten tracks.
The time required to trace one track is one tenth of one frame period. FIG. 3 shows data which is transmitted during one track period. As shown in FIG. 3, one track period is 3.33 milliseconds. During this period, all the data recorded in the above-mentioned areas, namely, the ITI, the audio area, the video area and the subcode area are transmitted. The head switch pulse is a reference signal for track recording by the DVTR. Cylinder servo is applied according to this head switch pulse.
In the case of the SD format of a home digital VTR, data is recorded on each track using one sync block as a recording unit. Each sync block is 90 bytes in length and contains 2-byte synchronizing signal (SYNC) and 3-byte ID.
The video area shown in FIG. 1 contains 2-byte SYNC, 3-byte ID, 77-byte video data area, 8-byte horizontal parity C1 and 77-byte vertical parity C2. The video area contains three video auxiliary data areas (VAUX0, VAUX1 and VAUX2), each being one-sync-block long, 135-sync-block long video data area and 11-sync-block long vertical parity C2.
The DVTR can record not only an analog TV signal after compressing it but also a digital data directly. FIG. 4 is a block diagram of the art relating to the DVTR which inputs and outputs digital data only.
IEEE (The Institute of Electrical and Electronics Engineers, Inc.) 1394 which is a low-cost peripheral interface suitable for multimedia applications is now widespread as the unified standards of a digital interface system for data transmission/reception among digital image devices. The IEEE 1394 makes it possible to multiplex a plurality of channels. The IEEE 1394 has an isochronous transfer function which guarantees the transfer of image, audio data, etc., within a given time, so it is the digital interface suitable for image transmission. Published Unexamined Patent Application No. 8-279818 (No. 279818/1996) discloses the IEEE 1394 in detail.
With the device shown in FIG. 4, a cable conforming to the IEEE 1394 standards is connected with a terminal 1. A 1394 circuit 2 is used to control a link layer and a physical layer of a digital interface conforming to the IEEE 1394 standards. The circuit receives data flowing on the 1394 cable (not shown) connected with the terminal 1 and sends the data to a digital I/F packet converter circuit 3, and at the same time sends data from this packet converter circuit 3 to the 1394 cable.
The digital I/F packet converter circuit 3 converts a packet conforming the IEEE 1394 standards into a packet conforming to the SD standards and vice versa. The 1394 packet is converted into the SD standards packet by the digital I/F packet converter circuit 3 to be fed to a correcting encoding/decoding circuit 5. In the case of the SD standards, the digital I/F converter circuit 3 converts a one-sync-block long data input into one DIF (Digital Interface) block. At the same time, this converter circuit converts one-track data into a 150 DIF block. The data is input/output in a 150-DIF-block unit.
In addition, the output of the digital I/F packet converter circuit 3 is rearranged by, for example, the correcting encoding/decoding circuit 5 into a data sequence shown in FIG. 1. The correcting encoding/decoding circuit 5 reads out data stored in a memory 6, arranges the vertical parity C2 (outside code) for error correction for the data arranged in the track direction in FIG. 1, and arranges the horizontal parity C1 (inside code) for the data arranged in the sync direction. The error correcting encoding/decoding circuit 5 adds the outside code and the inside code to the data and outputs the data in the format sequence shown in FIG. 1 to a modulator/demodulator circuit 7. This error correction processing is controlled by a microcomputer 10.
The output of the error correcting encoding/decoding circuit 5 is modulated by the modulator/demodulator circuit 7 and is recorded on the tape 9 by an amplifier equalization detecting circuit 8.
As described above, in the case of the SD standards, one frame is recorded on ten tracks. However, the SD standards do not permit a change to part of the content of the system data in one-frame recording unit. It is impossible to change the data from any track in one frame.
The Home Digital VTR Council is determined to adopt MPEG 2 system as a compression system for the next-generation digital broadcasting, ATV and DVB. The ATV standards and the DVB standards adopt a system which records data compressed by the MPEG 2 system as it is. The SD standards and the HD standards adopt an in-frame compression system. The MPEG 2 system adopts not only in-frame compression but also interframe compression coding. That is, MPEG 2 data has no fixed frame length, and the number of the tracks required for one-frame data recording is variable. Therefore, data is recorded in a track unit, and the subcode, the VAUX and the AAUX are also recorded in a track unit. Accordingly, in this case, the error correcting encoding/decoding circuit 5 can correct an error in a memory which can store data for a few tracks.
That is, in the error correction processing, first, the outside code (C2) is encoded, then the inside code (C1) is encoded for data containing such is encoded outside code. Therefore, it is necessary for the error correcting encoding/decoding circuit 5 first to store data recorded in the track direction which is required to generate such an outside code in order to add the outside code to the data. Accordingly, to encode the outside code, two memories are required: one memory which can store one-track data and another memory which can store one-track data to generate the outside code after reading the data from the above-mentioned memory.
Since the inside code is encoded in a sync block unit, this encoding process can be performed simultaneously with the output process to the modulator/demodulator circuit 7. These processings are performed cyclically for data sequentially input in a track unit. So, by using each memory of one-track capacity for each processing described above, the input and the outside code addition as well as the inside code addition and the output can be performed by a memory which can store n-track data.
As described above, the device shown in FIG. 4 can store digital data of a plurality of standards,
Transmission protocol and synchronizing procedure among different standards such as the MPEG 2 standards and the DVTR standards are now being standardized in the IEC 1883.
With the present protocol draft, a transmission side converts isochronous data into an isochronous packet conforming to the IEEE 1394 standards before transmitting the data. When this data having the same timing as that of a reference signal of the original data to be transmitted, for example, a data group containing a head data of one frame is converted into a packet, and a flag such as a frame pulse indicating a reference signal is inserted in the header data of the isochronous packet.
A reception side extracts the header flag of a received packet to adjust a frame start timing by the flag indicating the head of one frame. By so doing, it is possible to synchronize the transmission side with the reception side.
FIG. 5 is a timing chart showing the synchronization process described above. FIG. 5 shows the synchronization process among a plurality of devices. FIG. 5 shows the following processings etc. from top to bottom: a 1394 packet; a receiver A head switch pulse, an error correction processing and a recording processing; a receiver B head switch pulse (B), an error correction processing (B) and a recording processing (B); and a receiver C head switch pulse (C), an error correction processing (C) and a recording processing (C).
As described above, on the reception side DVTR, a delay time of n-track periods usually occurs in the error correction processing in the error correcting encoding/decoding circuit 5 shown in FIG. 4. That is, the output of the digital I/F packet converter circuit 3 shown in FIG. 4 is recorded on the tape 9 with the delay time of n-track periods due to the error correction processing and the recording processing. FIG. 5 shows an example one head switch pulse period. As shown in this Fig., two tack periods (the recording processing delay time in FIG. 5) is required for the error correction processing.
A cylinder rotation servo operates according to the head switch pulse (FIG. 5) indicating one track period as a reference signal. The data output timing from the modulator/demodulator circuit 7 to the amplifier equalization detecting circuit 8 is regulated by the head switch pulse. The present processing rate of the modulator/demodulator circuit is 24 bits, so the delay time due to modulation/demodulation processing can be ignored.
Therefore, the output timing of the error correcting encoding/decoding circuit 5 is almost equal to data recording timing on the tape 9. The timing is delayed by n-track period due to the error correction processing, so generally, as shown in FIG. 5, the input timing of the error correction processing is synchronized with the data recording start timing signal based on he head switch pulse as a reference signal.
For example, as shown in FIG. 5, the receiver A sends the output of the digital I/F packet converter circuit 3 based on the 1394 packet to the error correcting encoding/decoding circuit 5 at the head switch pulse timing to start the error correction processing. The error correction processing requires two track periods. Data is magnetically recorded on the tape 9 from the amplifier equalization detecting circuit 8, two track periods later from the input to the error correcting encoding/decoding circuit 5. As shown in FIG. 5, the receivers B and C perform the error correction processing and the recording processing at the timing according to the head switch pulses (B) and (C) of these receivers.
As described above, the error correction input processing is performed synchronously with the head switch pulse of each receiver A, B and C. So it is necessary to hold the input 1394 packet for the delay time shown in FIG. 5. Therefore, the device shown in FIG. 4 has a buffer memory 4. The digital I/F packet converter circuit 3 uses the buffer memory 4 to synchronize the output to the error correcting encoding/decoding circuit 5 with the head switch pulse.
To dub data from one DVTR to another DVTR, a DVTR on the reception side records one-frame data on 10 tracks. Therefore, it is necessary to record a frame head data on the first tack of these 10 tracks.
To synchronize digital data to be input into the DVTR with the tape so that such data is recorded at the tape recording start position, namely, at the head track of one frame, two methods, namely, synchronization on the reception side and synchronization on the transmission side are available.
Let us assume that a DVTR on the recording side is going to start data recording at a certain point on a recorded tape. Then, it is necessary to start data recording at the head track of one frame, namely, at a track (hereinafter called a head track) which continues with data already recorded on a frame unit (in a 10-track unit) in order to record a tracking pilot signal for synchronizing a servo.
FIG. 6 is a diagram for illustrating the tracking pilot signal.
With the embodiment shown in FIG. 6, three signals having the frequencies f0, f1 and f2 (hereinafter called pilot signals F0, F1 and F2) are used as a tracking pilot signal. These pilot signals F1, F0, F2, F0, F1, F0, F2, F0, . . . are recorded sequentially and overlappedly. In reproduction, the levels of the pilot signals F1 and F2 contained in reproduced signals are compared. It is so controlled that the track phase coincides with a track on which the pilot signal F0 is superimposed. In this case, taking the deviated direction of the track phase into consideration, the track phase can be coincided with the track of the pilot signal F0 at every fourth track.
If data recording starts at any track other than the head track of each frame shown in FIG. 6, then the pilot signals are arranged in an incorrect order and the tracking servo does not function normally. Therefore, it is necessary to start new data recording from a track (head track shown in FIG. 6) next to the last track of the last frame of data previously recorded.
With synchronization on the reception side, the receiver should be set in standby mode at the last track of the frame of data already recorded. That is, tape transport should be stopped but the cylinder should be kept rotating while synchronizing the servo with the reference signal (the head switch pulse). Here too, the frame reference signal (the frame pulse) must be kept being generated to start data recording at a head frame.
With the receiver kept in standby mode, a transmitter sends data through the 1394 cable. The receiver shown in FIG. 4 first receives data, then holds the data so that the output of the error correcting encoding/decoding circuit 5 starts at a timing n-track (two tracks in FIG. 5) prior to the head track using a buffer memory 4. The digital I/F packet converter circuit 3 outputs data read out from the buffer memory 4 to the error correcting encoding/decoding circuit 5 at a position n-track prior to the head track. When the head track position is reached, the transport of the tape 9 starts, and the recorded data from the amplifier equalization detecting circuit 8 is recorded on the tape 9. By so doing, data at the head of a frame can be recorded properly from the head track.
However, when using this method, the buffer memory 4 should have a capacity to store data up to one frame (10 tracks), so circuit scale becomes large.
With synchronization on the transmission side, a transmitter may adjust the transmission timing. That is, the transmitter may adjust the transmission timing so that the receiver can receive data at a position n-track prior to a head frame so as to record data at a head frame. With this method, the receiver may use a buffer memory of relatively small capacity as a buffer memory 4 for adjusting data input timing to the error correcting encoding/decoding circuit 5.
However, no protocol suitable for this method is available.
In addition, this method may be used when that data is exchanged between one transmitter and one receiver. However, as shown in FIG. 5, this method may not be used in such a case that a plurality of receivers receive data from one transmitter. That is, as shown in FIG. 5, the reference signal (the head switch pulse) of each receiver is generated independently of each other and the position of the head track of each receiver is different from each other. Therefore, if the transmitter sends out data synchronously with one receiver, data received by other receivers is not synchronized with their reference signal. The frame reference signal reception positions of these receivers are different from each other by up to one frame, so any receiver which has received synchronized data must have a buffer memory whose capacity is up to one frame.
To transmit data synchronously with all the receivers from the transmission side, a transmitter must be equipped with frame memories in the number corresponding to the number of the receivers.
Using an alternate synchronizing method, a servo reference signal may be inserted in isochronous data. Thus, on the reception side, synchronization is achieved using a servo reference signal.
However, the receiver starts servo pull-in operation after receiving isochronous data, so a relatively long time is required until the servo phases of all the receivers are locked. Therefore, it is necessary for each receiver to hold the data in the buffer once until the phases coincide with each other. Therefore, a memory with large capacity is required as a buffer memory.
As described above, to record transmitted digital data, a buffer memory with large capacity is required for synchronization resulting in increased circuit scale.
To record received data from a correct recording start position, a buffer memory with large capacity is required resulting in increased circuit scale.
To record received data at a position just after data previously recorded without an unnatural gap, a buffer memory with large capacity is required resulting in increased circuit scale.
To dub data synchronously by a plurality of devices, a buffer with large capacity is required resulting in increased circuit scale.
It is an object of the present invention to provide an apparatus having a digital interface which can record data synchronously, can record new data at a position just after data previously recorded without an unnatural gap and can perform a synchronous dubbing operation by a plurality of devices without using a buffer memory with large capacity and a digital interfacing method.
One aspect of the present invention is to provide an apparatus having a digital interface that comprises a timing reference signal transmitting means which is installed in one or more first devices in a network comprising a plurality of devices, converts an original timing reference signal into first data to be transmitted synchronously and sends out the data to a transmission path forming the network; a timing reference signal generating means which is installed in a second device other than the first device(s) in the network and generates a timing reference signal based on the original timing reference signal transmitted through the transmission path; a transmitting means which is installed in a device in the network, converts a predetermined transmitted data into second data to be synchronously transmitted, synchronously with the original timing reference signal of the timing reference signal and sends out the resulting data to the second data to be synchronously transmitted through the transmission path, and records the recorded data synchronously with the original timing reference signal or the timing reference signal.
In this apparatus, the original timing reference signal is converted into the first data to be synchronously transmitted by the original timing reference signal transmitting means of the first devices(s) and is sent out to the transmission path. The timing reference signal generating means of the second devices other than the first devices receives the transmitted original timing reference signal and obtains its own timing reference signal. By this signal, the second devices other than the first device(s) are synchronized with each other. A device equipped with the transmitting means converts predetermined transmitted data into the second data to be synchronously transmitted according to the original timing reference signal or the timing reference signal and sends out the resulting data to the transmission path. The second data to be synchronously transmitted is received by the receiving means of the receiving device and recorded synchronously with the original timing reference signal or the timing reference signals. Both the device having the transmitting means and the device having the recording means are synchronized according to the original timing reference signal, so they can record new data synchronously or continuously just after data previously recorded without an unnatural gap.
Another aspect of the present invention is to provide a digital interfacing method that comprises a timing reference signal transmitting procedure in which an original timing reference signal from one or more first devices in a network comprising a plurality of devices is converted into first data to be synchronously transmitted and the resulting data is sent out to a transmission path in the network; a synchronizing procedure in which the original timing reference signal transmitted through the transmission path is receive by a second device other than the first device(s) in the network and synchronized with the received signal by obtaining a recording timing reference signal based on the transmitted original timing reference signal; a transmitting procedure in which a predetermined transmission data is converted into the second data to be synchronously transmitted by the device in the network according to the original timing reference signal or the timing reference signal and sent out to the transmission path; and a recording procedure in which the second data to be synchronously transmitted is received by the device in the network through the transmission path and is synchronized with th original timing reference signal or the timing reference signal to record it.
In this method, the first data to be synchronously transmitted that is based on the original timing reference signal and the timing reference signal is sent out from the first device(s) to the transmission path. The second device other than the first device(s) obtains a timing reference signal based on the transmitted original timing reference signal. By this timing reference signal, the devices in the network are synchronized with each other. When such synchronization is achieved, the device on the transmission side sends out the second data to be synchronously transmitted based on the transmission data to the transmission path. This transmission is made synchronously with the original timing reference signal or timing reference signal. The device in the reception side receives second data to be synchronously transmitted, synchronously with the original timing reference signal or timing reference signal and records the received data. By so doing, a plurality of data can be synchronously recorded and new data recording can be started at a position just after data previously recorded without an unnatural gap.